Epitaxially deposited source/drain

ABSTRACT

An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/692,696, filed on Oct. 24, 2003.

BACKGROUND

This invention relates generally to metal oxide semiconductor fieldeffect transistors.

Metal oxide semiconductor field effect transistors include a gate thatis self-aligned with a source/drain. The source/drain may include adeeper or heavily doped region and a shallower and lightly doped region,sometimes called a tip or source/drain extension.

Gate underlap is the amount by which the source/drain material diffusesunder the gate after ion implantation and subsequent heat processing.After implantation, the material that is implanted is exposed to heatwhich causes the material to move downwardly into the substrate and, toa lesser extent, laterally under the gate. Thus, in a system using anion implanted source/drain extension, the amount of underdiffusion isdetermined as a function of junction depth.

It is desirable to have relatively shallow junction depth for thesource/drain extension to support smaller transistor dimensions.Usually, in source/drain extension implantation techniques, the minimumtip junction depths are determined by the necessary gate underlap.

The shallower the source/drain extension, generally the shorter the gatelengths that may be utilized without increasing off-state leakagecurrents. Extension doping under the gate edge is needed to ensure a lowresistance path between the inversion layer under the gate and thehighly doped source/drain extension region. The low resistance is neededfor a high drive currents, which are critical for high circuit switchingspeeds.

Thus, there is a need for better ways to make source/drain junctions offield effect transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a greatly enlarged, cross-sectional view at one stage ofmanufacture;

FIG. 2 is an enlarged, cross-sectional view at a subsequent stage ofmanufacture in accordance with one embodiment of the present invention;

FIG. 3 is an enlarged, cross-sectional view at still a subsequent stageof manufacture in accordance with one embodiment of the presentinvention;

FIG. 4 is an enlarged, cross-sectional view at a subsequent stage ofmanufacture in accordance with one embodiment of the present invention;and

FIG. 5 is an enlarged, cross-sectional view at still a subsequent stageof manufacture in accordance with one embodiment of the presentinvention.

DETAILED DESCRIPTION

Referring to FIG. 1, a heavily doped semiconductor substrate 12 may becovered by a sacrificial, undoped, or lightly doped epitaxial siliconlayer 18. The layer 18 may be less than 500 Angstroms thick in oneembodiment. A gate electrode structure including a gate 16 formed over agate dielectric 14 may be defined on the epitaxial silicon layer 18.

The selective deposition of the sacrificial epitaxial silicon layer 18may be carried out, for example, using dichlorosilane-based chemistry ina single wafer chemical vapor deposition reactor, such as an Epsilon3000 epitaxial reactor, available from ASM International NV, Bilthoven,Netherlands. The film may be deposited with gas flows of 150-200 sccm ofdichlorosilane, 100-150 sccm of HCl, 20 slm of H₂ at 825° C. in aprocessed pressure of 20 Torr. Under these processing conditions, adeposition rate of 10-15 nanometers per minute may be achieved forsilicon on exposed substrate while achieving selectivity to spacer andoxide regions. Other deposition techniques may also be used.

The arrangement shown in FIG. 1 is sometimes called a delta dopedtransistor. Because there is relatively high doping below the epitaxiallayer 18, a large delta or change in concentration occurs at theinterface between the substrate 12 and the epitaxial silicon layer 18.

The structure shown in FIG. 1 may be covered by a spacer material andthen anisotropically etched to form the sidewall spacers 28 shown inFIG. 2. Some limited etching of the epitaxial silicon 18 may occur atthe same time depending on the selectivity of the spacer etch.

After spacer formation, a selective wet etch may remove the exposedportions of the epitaxial silicon layer 18 and may continue etchingunder the gate 16 to achieve the undercut structure shown in FIG. 3. Theextent of gate 16 undercut can be controlled by adjusting the etch time.

The epitaxial silicon layer 18 may be selectively etched with a varietyof hydroxide-based solutions, for example. However, for high selectivityof the undoped or lightly doped layer 18 to the heavily doped substrate12, relatively mild processing conditions may be employed.

In one embodiment, an aqueous ammonium hydroxide solution in theconcentration range of 2 to 10 percent by volume at 20° C. may be usedtogether with sonication. The sonication may be provided by a transducerthat dissipates ultra or megasonic energy with a power of 0.5 to 5 wattsper cm² in one embodiment of the present invention. Since the deltadoped transistor has a heavily doped region below the undoped region, itmay serve as an etch stop layer for the wet etch.

After the wet etch undercut, a doped selective epitaxial silicon layer50 may be grown. A shallow, highly doped source/drain extension 50 alaterally extends the desired distance under the gate 16 edge and thesidewall spacer 28, as shown in FIG. 4. A thicker source/drain region 50b is aligned with the edge of the spacer 28 and extends away from thespacer 28. The spacer 28 enables the length of the extension 50 a to betailored and allows the thickness of the layer 50 to expand withoutshorting to the gate 16. The thicker region 50 b reduces resistance ofthe region 50 and brings the lower resistance region close to the edgeof the gate 16.

In forming the P-type MOS (PMOS) transistor, the source/drain extension50 a and raised source/drain 50 b may be formed by selectivelydepositing epitaxial boron doped silicon or silicon germanium with agermanium concentration of up to 30 percent, as one example. Under theprocessing conditions of 100 sccm of dichlorosilane, 20 slm H₂, 750-800°C., 20 Torr, 150-200 sccm HCl, diborane flow of 150-200 sccm and GeH₄flow of 150-200 sccm, a highly doped silicon germanium film with adeposition rate of 20 nanometers per minute, a boron concentration of1E20 cm⁻³, and a germanium concentration of 20 percent may be achievedin one embodiment. A low resistivity of 0.7-0.9 mOhm-cm results from thehigh boron concentration of the film.

Low resistivity provide the benefit of high conductivity in theextension and source/drain regions in some embodiments. This loweredresistivity may reduce the external resistance. The larger unit cell ofthe silicon germanium present in source/drain regions 50 b may exertcompressive strain on the channel, which in turn may result in enhancedmobility and transistor performance in some embodiments.

In the N-type transistor (NMOS), the source/drain 50 b and source/drainextension 50 a may be formed using in situ phosphorus doped silicondeposited in one embodiment. The silicon may be deposited selectivelyunder processing conditions of 100 sccm of dichlorosilane, 25-50 sccmHCl, 200-300 sccm of 1 percent PH₃ with a H₂ gas carrier flow of 20 slmat 750° C. and 20 Torr. A phosphorous concentration of 2E20 cm⁻³ with aresistivity of 0.4-0.6 mOhm-cm may be achieved in the deposited film inone embodiment.

Thereafter, a second thin spacer 34 may be formed using conventionaltechniques as shown in FIG. 5. A deep source/drain 32 may be formed byion implantation using the spacers 28 and 34 and the gate 16 as a mask.The annealing of the deep source/drain 32 may be done in a way thatreduces or minimizes the dopant diffusion including the dopant in thelayer 50.

The characteristics of the shallow source/drain extensions 50 a and thedegree by which they underlap the gate 16 may be independent of thecharacteristics of the deep source/drain junction 32. The extent ofextension underlap of the gate 16 of the source/drain extension 50 a maybe controlled as desired.

While the present invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit and scope of this present invention.

1. A field effect transistor comprising: a substrate; a doped epitaxialsemiconductor material formed over said substrate; and a gate electrodeformed over said doped epitaxial semiconductor material, said dopedepitaxial semiconductor material extending under said gate electrode. 2.The transistor of claim 1 including a source/drain having a source/drainextension, said source/drain extension being formed of said dopedepitaxial semiconductor material and extends under the edges of the gateelectrode.
 3. The transistor of claim 2 wherein said material has afirst thickness near said gate electrode and a second thickness spacedfrom said gate electrode, said second thickness being greater than saidfirst thickness.
 4. The transistor of claim 3 including a sidewallspacer, said material extending under said sidewall spacer.
 5. Thetransistor of claim 4 wherein said second thickness is aligned with saidsidewall spacer.
 6. The transistor of claim 1 wherein said transistor isa delta doped transistor.
 7. The transistor of claim 1 including an ionimplanted source/drain under said doped epitaxial semiconductormaterial.